发明名称 Low-latency viterbi survivor memory architecture and method using register exchange, trace-back, and trace-forward
摘要 In various aspects, the disclosure describes systems and methods for decoding of convolutionally encoded signals representing, for example, telecommunications signals such as command or content signals used in digital telecommunications. In various embodiments such aspects of the disclosure provide systems and methods for improving the efficiency, speed, and power consumption of such processes by providing architectures and methods for processing various parts of the encoded data records in parallel, using multiple and optionally specially-designed, dedicated memory registers and multiplexers.
申请公布号 US8433004(B2) 申请公布日期 2013.04.30
申请号 US20100713502 申请日期 2010.02.26
申请人 KOSAKOWSKI MARTIN;RESEARCH IN MOTION LIMITED 发明人 KOSAKOWSKI MARTIN
分类号 H04L27/06 主分类号 H04L27/06
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