| 摘要 |
A data signal loading circuit (i) which includes: a comparator CMP1 receiving clock signal CKP and reverse-phase signal CKN of clock signal CKP, and outputting clock signal CLP1 which is in phase with clock signal CKP, and clock signal CLN 1 having a reverse phase of clock signal CKP; a comparator CMP 2 having a non-inverting input terminal receiving clock signal CLP1, and an inverting input terminal receiving clock signal CLN1; and a comparator CMP3 having an inverting input terminal receiving clock signal CLP 1, and a non-inverting input terminal receiving clock signal CLN 1, and (ii) which, by using output signals CL1 and CL2 of the comparator CMP2 and the comparator CMP3 as clock signals for latch circuits L1 and L2, equalizes delay times for the rise or fall of clock signals CL1 and CL2 inputted to the latch circuits L1 and L2, and (iii) has low power consumption. |
