| 摘要 |
A wire bond chip package (100, 100a, 100b, 100c) includes a chip carrier (40, 140, 240); a semiconductor die (10) having a die face (10a) and a die edge (10c), the semiconductor die (10) being mounted on a die attach surface (40a, 140a) of the chip carrier, wherein a plurality of input/output (I/O) pads (12) are situated in or on the semiconductor die; a rewiring laminate structure (20) on the semiconductor die, the rewiring laminate structure comprising a plurality of redistribution bond pads (22); a plurality of bond wires (50) interconnecting the redistribution bond pads (22) with the chip carrier (40, 140, 240); and a mold cap (60) encapsulating at least the semiconductor die (10) and the bond wires (50). |
