ASYMMETRIC STATIC RANDOM ACCESS MEMORY CELL WITH DUAL STRESS LINER

摘要

A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Each memory cell includes a pair of cross-coupled CMOS inverters, and corresponding pass gates for coupling the cross-coupled storage nodes to first and second bit lines. Asymmetry is incorporated into each memory cell by constructing one of the inverter transistors or the pass-gate transistor using the stress liner with opposite stress characteristics from its opposing counterpart. For example, both of the p-channel load transistors and one of the n-channel driver transistors in each memory cell may be constructed with a compressive nitride liner layer (40C) while the other driver transistor is constructed with a tensile nitride liner layer (40T). In another implementation, one of the n-channel pass-gate transistors is constructed with a compressive nitride liner layer (40C) while the other pass-gate transistor is constructed with a tensile nitride liner layer (40T). Improved cell stability due to the resulting asymmetric behavior is implemented in a cost-free manner.