发明名称 |
Implementing single bit redundancy for dynamic SRAM circuit with any bit decode |
摘要 |
A method and a dynamic Static Random Access Memory (SRAM) circuit for implementing single bit redundancy with any bit decode, and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a plurality of bitline columns and a pair of redundancy columns respectively coupled to a respective merged bit column select and redundancy steering multiplexer. Each merged bit column select and redundancy steering multiplexer receives a respective select signal input. A select signal generation circuit receives a redundancy steering signal and a respective one-hot bit select signal, generating the respective select signal input. |
申请公布号 |
US8427894(B2) |
申请公布日期 |
2013.04.23 |
申请号 |
US20100886692 |
申请日期 |
2010.09.21 |
申请人 |
BEHRENDS DERICK G.;CHRISTENSEN TODD A.;FREIBURGER PETER T.;HEBIG TRAVIS R.;WITTRUP JAYSON K.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BEHRENDS DERICK G.;CHRISTENSEN TODD A.;FREIBURGER PETER T.;HEBIG TRAVIS R.;WITTRUP JAYSON K. |
分类号 |
G11C29/04;G06F17/50 |
主分类号 |
G11C29/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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