发明名称 Control circuit and method for reducing output ripple in constant on-time switching regulator
摘要 The present invention discloses a control circuit for reducing output ripple in a constant on-time switching regulator and a method thereof, for controlling a power stage. The control circuit determines whether a zero current period wherein an output current is zero is longer than a threshold period, and switches the on-time period to a shorter period if it is longer, whereby the power stage operates according to the shorter period while still in the discontinuous conduction mode (DCM).
申请公布号 US8427128(B2) 申请公布日期 2013.04.23
申请号 US201113134994 申请日期 2011.06.22
申请人 TSAI YU-NUNG;RICHTEK TECHNOLOGY CORPORATION, R.O.C. 发明人 TSAI YU-NUNG
分类号 G05F1/46;G05F1/575 主分类号 G05F1/46
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