发明名称 ADDRESS TRANSLATION DEVICE, ARITHMETIC PROCESSING DEVICE AND CONTROL METHOD OF ARITHMETIC PROCESSING DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To provide an address translation device capable of inhibiting occurrence of unnecessary memory access when retrieving a page table. <P>SOLUTION: An address translation device comprises: a translation lookaside buffer (TLB) which stores a set of a virtual address and a physical address for each page size and performs address translation; a storage part which stores a set of a virtual address put out from the TLB and a corresponding page size when a new set of a virtual address and a physical address read from a page table is registered in the TLB; and a base register which stores a page address for each page size. If a retrieval error occurs when the TLB is retrieved based on a virtual address of a translation object included in a memory access request, the virtual address of the translation object is translated to a physical address by retrieving main memory on the basis of a pointer address generated from information stored in the storage part and the base register. By this way, occurrence of unnecessary memory access is inhibited. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013073270(A) 申请公布日期 2013.04.22
申请号 JP20110209755 申请日期 2011.09.26
申请人 FUJITSU LTD 发明人 KIMURA HIROAKI
分类号 G06F12/10 主分类号 G06F12/10
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