发明名称 |
MEMORY UNIT, INFORMATION PROCESSING DEVICE, AND METHOD |
摘要 |
A memory unit comprises at least two volatile memory elements, analyzing circuitry and power gate. The memory elements may for example be latches, flip-flops, or registers. Each of the memory elements has at least two different states including a predefined reset state. The analyzing circuitry generates a power-down enable signal in response to each of the memory elements being in its reset state. The power gate powers down the memory elements in response to the power-down enable signal. The memory elements may be arranged to assume their reset states upon powering up the memory unit. |
申请公布号 |
US2013097449(A1) |
申请公布日期 |
2013.04.18 |
申请号 |
US201013634755 |
申请日期 |
2010.06.11 |
申请人 |
PRIEL MICHAEL;RABINOWICZ JOSEPH;ROZEN ANTON;FREESCALE SEMICONDUCTOR, INC. |
发明人 |
PRIEL MICHAEL;RABINOWICZ JOSEPH;ROZEN ANTON |
分类号 |
G06F1/32;G11C5/14 |
主分类号 |
G06F1/32 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|