| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an arithmetic processing unit for performing efficient thread selection. <P>SOLUTION: The arithmetic processing unit includes: first selectors (SL1 to SLn) for selecting instruction addresses of a plurality of threads or branch destination address of a branch instruction as an object of prediction, and for outputting addresses of the plurality of threads; a second selector (313) for selecting one of the addresses of the plurality of threads output by the first selectors; a branch prediction circuit (204) for predicting and outputting a branch direction showing whether or not the branch instruction of the address selected by the second selector is branched on the basis of the selected address in a first cycle stage, and for predicting and outputting the branch destination address of the branch instruction as the object of prediction on the basis of the selected address in a second cycle stage posterior to the first cycle stage; and a threshold arbitration circuit (311) for controlling the first selector and the second selector to select the address of the thread on the basis of the branch direction output by the branch prediction circuit. <P>COPYRIGHT: (C)2013,JPO&INPIT |
