发明名称 IMAGE COMPRESSION APPARATUS AND IMAGE PROCESSING SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To reduce band width and latency when data to be expanded is read from a memory irrespective of a size of a block line. <P>SOLUTION: An image compression apparatus 10 in an embodiment writes compressed image data in a memory 20. The image compression apparatus 10 includes a compression section 12, a written address determining section 14 and a memory control section 16. The compression section 12 divides original image data including a plurality of pixels into a plurality of block lines, divides each of the block lines into a plurality of sub-block lines, compresses the original image data for each sub-block line and generates a plurality of compressed sub-block lines. The written address determining section 14 determines a written address of the memory 20 for each compressed sub-block line on the basis of the number of sub-block lines, an original image data size of the original image data and an image compression rate. The memory control section 16 writes the plurality of compressed sub-block lines in the written addresses corresponding to the respective compressed sub-block lines. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013070321(A) 申请公布日期 2013.04.18
申请号 JP20110208845 申请日期 2011.09.26
申请人 TOSHIBA CORP 发明人 UCHIYAMA MASATO
分类号 H04N19/00;H04N1/41;H04N19/102;H04N19/134;H04N19/136;H04N19/169;H04N19/176;H04N19/182;H04N19/423;H04N19/426;H04N19/50 主分类号 H04N19/00
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