发明名称 |
Finfet Parasitic Capacitance Reduction Using Air Gap |
摘要 |
Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers.
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申请公布号 |
US2013095629(A1) |
申请公布日期 |
2013.04.18 |
申请号 |
US201213617426 |
申请日期 |
2012.09.14 |
申请人 |
ANDO TAKASHI;CHANG JOSEPHINE B.;KANAKASABAPATHY SIVANANDA K.;KULKARNI PRANITA;STANDAERT THEODORUS E.;YAMASHITA TENKO;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ANDO TAKASHI;CHANG JOSEPHINE B.;KANAKASABAPATHY SIVANANDA K.;KULKARNI PRANITA;STANDAERT THEODORUS E.;YAMASHITA TENKO |
分类号 |
H01L21/336;H01L21/283 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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