发明名称 ERROR CORRECTION IN A STACKED MEMORY
摘要 Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed.
申请公布号 US2013097471(A1) 申请公布日期 2013.04.18
申请号 US201213692812 申请日期 2012.12.03
申请人 MICRON TECHNOLOGY, INC.;MICRON TECHNOLOGY, INC. 发明人 JEDDELOH JOE M.
分类号 H03M13/03 主分类号 H03M13/03
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