| 摘要 |
<p>Disclosed is an output buffer circuit whereby the time difference between the rise time and the fall time of various output voltages of a difference output signal can be reduced and furthermore precise coincidence can be achieved of the rise time and the fall time. PMOS transistors (Tr5, Tr6) are connected respectively in parallel with resistance elements (R1, R2). If the resistive components of the resistance elements (R1, R2) are designated as r1(Omega),r2(Omega), the resistive components of the PMOS transistors (Tr5, Tr6) are designated as (rTr5(Omega), rTr6(Omega)), and the resistive component of the current source (I1)is designated as rI1(Omega), then the conditions: (r1//rTr5)=(r2//rI1),(r2//rTr6)=(r1//rI1) are satisfied. In this way, the time difference between the rise time and the fall time of the various output voltages can be reduced, and, furthermore, the rise times and fall times can be made to coincide precisely.</p> |
