发明名称 INSTRUCTION-ISSUANCE CONTROLLING DEVICE AND INSTRUCTION-ISSUANCE CONTROLLING METHOD
摘要 In a multithread processor capable of executing a plurality of threads, in order to select a thread and instruction for increasing a throughput of the multithread processor, an instruction-issuance controlling device included in the multithread processor includes a resource management unit configured to manage stall information indicating whether or not each of threads in execution is in a stalled state; a thread selection unit configured to select a thread which is not in the stalled state among the threads in execution; and an instruction-issuance controlling unit configured to perform controlling so that simultaneously issuable instructions are issued from among the selected thread.
申请公布号 US2013097409(A1) 申请公布日期 2013.04.18
申请号 US201213692141 申请日期 2012.12.03
申请人 PANASONIC CORPORATION;PANASONIC CORPORATION 发明人 YAMANA TOMOHIRO
分类号 G06F9/30 主分类号 G06F9/30
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