发明名称
摘要 401 stores, in 302, key d' obtained by subtracting random number 2r held in 201 from key d held in 105. When an operation starts, the values "-C" and "-C2" are calculated respectively, and the resultant values are stored in a multiplication table memory 205 together with value "C". In a first operation cycle, 107 selects and outputs an intermediate value 108 held in an in-operation data register 103, and thereby makes a modular-multiplication operation circuit 104 perform squaring. In the second operation cycle, 107 selects and outputs one of three values held in 205 in accordance with the combination of key bit value d'i and random number bit value ri, and thereby makes the modular-multiplication operation circuit 104 perform multiplication. Thereby, a cryptographic processing device that requires a short operation time period, small circuit scale, and has sufficient security can be realized.
申请公布号 JP5182364(B2) 申请公布日期 2013.04.17
申请号 JP20100505038 申请日期 2008.03.28
申请人 发明人
分类号 G09C1/00;H04L9/10 主分类号 G09C1/00
代理机构 代理人
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