发明名称 |
Seamless coarse and fine delay structure for high performance DLL |
摘要 |
A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.
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申请公布号 |
US8421515(B2) |
申请公布日期 |
2013.04.16 |
申请号 |
US201113341418 |
申请日期 |
2011.12.30 |
申请人 |
KWAK JONGTAE;KIM KANG YONG;MICRON TECHNOLOGY, INC. |
发明人 |
KWAK JONGTAE;KIM KANG YONG |
分类号 |
H03K5/159;H03L7/00;H03L7/06 |
主分类号 |
H03K5/159 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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