发明名称 Multi level inhibit scheme
摘要 Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and maintained through capacitive coupling with word lines coupled to the memory cells and biased to predetermined bias levels. Methods of manipulation of isolated channel region bias levels through applied word line bias voltages affecting a program inhibit effect, for example, are also disclosed.
申请公布号 US8422297(B2) 申请公布日期 2013.04.16
申请号 US20100981688 申请日期 2010.12.30
申请人 TAMADA SATORU;MICRON TECHNOLOGY, INC. 发明人 TAMADA SATORU
分类号 G11C16/04;G11C11/40 主分类号 G11C16/04
代理机构 代理人
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