| 摘要 |
A memory chip is provided and includes a control unit, a wait controller, and a wait receiver. When the memory chip operates in an active mode and the control unit determines that the memory chip will be changed to operate in an inactive mode according to an input address signal, the wait controller changes a state of a wait signal at a wait pad from a de-asserted state to an asserted state. When the memory chip operates in an inactive mode and the wait receiver detects that the state of the wait signal has been changed from the de-asserted state to the asserted state, the control unit determines whether the memory chip will be changed to operate in the active mode or a word-line boundary crossing operation will be performed to another memory chip.
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