| 摘要 |
<p>PURPOSE: An array panel and a manufacturing method thereof are provided to prevent parasitic capacitance by reducing an overlapped area between a source/drain electrode and a gate electrode. CONSTITUTION: A source/drain electrode(133,136) touches a second area(105b) of an oxide semiconductor layer(105) through a first and a second semiconductor contact hole(122a,122b). An interlayer dielectric layer(120) is formed on a gate line and a gate electrode(116). The source/drain electrode is not overlapped with the gate electrode. The conductivity of the second area is larger than the conductivity of a first area(105a).</p> |
