| 摘要 |
A method and system optimizes or improves an electronic design by analyzing various signal paths in the electronic design and selecting certain critical paths, for example, failed-timing paths, to optimize. The optimizing method extracts the cascaded logic gates to create a megacell representing the function of the critical path, compare test parameters of the megacell with the critical path, and incorporate the megacell into the electronic design if the test parameters improve by an optimizing constraint.
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