发明名称 |
DIVIDER CIRCUIT |
摘要 |
A divider circuit includes a shift register which generates 2X (X is a natural number greater than or equal to 2) pulse signals in accordance with a first clock signal or a second clock signal and outputs them, and a divided signal output circuit which generates a signal to be a third clock signal with a cycle X times longer than a cycle of the first clock signal in accordance with the 2X pulse signals and outputs it. The divided signal output circuit includes X first transistors which control whether voltage of the signal to be the third clock signal is set to first voltage; and X second transistors which control whether voltage of the signal to be the third clock signal is set to second voltage. |
申请公布号 |
KR20130036229(A) |
申请公布日期 |
2013.04.11 |
申请号 |
KR20127028882 |
申请日期 |
2011.03.18 |
申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
发明人 |
TAKAHASHI KEI;ITO YOSHIAKI |
分类号 |
H03K3/356;H03K19/0175;H03K23/00;H03K23/54 |
主分类号 |
H03K3/356 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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