发明名称 JITTER SUPPRESSION IN TYPE I DELAY-LOCKED LOOPS
摘要 In one embodiment, a delay-locked loop (DLL) for synchronizing a phase of a periodic digital output signal with a phase of a periodic digital input signal includes a deskew element responsive to the periodic digital input signal to the DLL and the periodic digital output signal from the DLL for suppressing jitter in the periodic digital output signal by synchronizing transitions in the periodic digital output signal with transitions in the periodic digital input signal and generating a final jitter- suppressed periodic digital output signal.
申请公布号 WO2013052186(A2) 申请公布日期 2013.04.11
申请号 WO2012US43964 申请日期 2012.06.25
申请人 LIGHTWIRE LLC;WILSON, WILLIAM, BURDETT 发明人 WILSON, WILLIAM, BURDETT
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