发明名称 OVERLAY AND SEMICONDUCTOR PROCESS CONTROL USING A WAFER GEOMETRY METRIC
摘要 The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region.
申请公布号 US2013089935(A1) 申请公布日期 2013.04.11
申请号 US201213476328 申请日期 2012.05.21
申请人 VUKKADALA PRADEEP;VEERARAGHAVAN SATHISH;SINHA JAYDEEP K.;KLA-TENCOR CORPORATION 发明人 VUKKADALA PRADEEP;VEERARAGHAVAN SATHISH;SINHA JAYDEEP K.
分类号 H01L21/66;G01B9/02;G01B11/24 主分类号 H01L21/66
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