发明名称 Semiconductor memory apparatus, and circuit and method for controlling faulty address therein
摘要 A faulty address control circuit comprises a variable resistance fuse unit configured to be driven in response to an address signal, a resistance value of the variable resistance fuse unit being determined based on an amount of an applied current; a driving unit configured to output a driving signal based on the resistance value of the variable resistance fuse unit in response to a faulty address control signal; and an address storage and determination unit configured to receive the address signal, be driven by the driving signal to output the address signal or an inverted signal of the address signal.
申请公布号 US8416637(B2) 申请公布日期 2013.04.09
申请号 US20100836505 申请日期 2010.07.14
申请人 RIM WOO JIN;SK HYNIX INC. 发明人 RIM WOO JIN
分类号 G11C17/18 主分类号 G11C17/18
代理机构 代理人
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