发明名称 |
Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone |
摘要 |
An asymmetric insulated-gate field effect transistor (100U or 102U) provided along an upper surface of a semiconductor body contains first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima (316-1-316-3) at respective locations (PH-1-PH-3) spaced apart from one another. The tailoring is typically implemented so that the vertical dopant profile of the pocket portion is relatively flat near the upper semiconductor surface. As a result, the transistor has reduced leakage current. |
申请公布号 |
US8415752(B2) |
申请公布日期 |
2013.04.09 |
申请号 |
US201213348577 |
申请日期 |
2012.01.11 |
申请人 |
YANG JENG-JIUN;BULUCEA CONSTANTIN;BAHL SANDEEP R.;NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
YANG JENG-JIUN;BULUCEA CONSTANTIN;BAHL SANDEEP R. |
分类号 |
H01L29/78 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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