MULTILAYER PRINTED CIRCUIT BOARD WITH INTERSTITIAL VIA HOLE STRUCTURE FOR REDUCED PARASTIC CAPACITANCES
摘要
PURPOSE: A multilayer printed circuit board with an interstitial via structure with reduced parasitic capacitance is provided to enable a user to easily design a substrate by using an interstitial via hole. CONSTITUTION: A via plating body(110) includes a top pad and a bottom pad. A first metal plate(120) is parallel to one of the top pad and the bottom pad and includes a hole in a normal direction to one of the top pad and the bottom pad. A first dielectric(130) is arranged between the first metal plate and one of the top pad and the bottom pad. A strip line(140) is horizontally connected to one of the top pad and the bottom pad.
申请公布号
KR101252999(B1)
申请公布日期
2013.04.09
申请号
KR20110127698
申请日期
2011.12.01
申请人
SAMSUNG ELECTRO-MECHANICS CO., LTD.;SOONGSIL UNIVERSITY RESEARCH CONSORTIUM TECHNO-PARK
发明人
KIM, BOO GYOUN;WEE, JAE KYUNG;YOON, YOUNG MIN;CHUNG, YUL KYO;KIM, HYUN HO;RYU, JONG IN