发明名称 Circuit and method for generating body bias voltage for an integrated circuit
摘要 A circuit includes a PMOS body bias circuit including a PMOS charge pump for generating a positive supply voltage, a PMOS reference voltage generator for providing a PMOS reference voltage, and a PMOS linear voltage regulator circuit for generating a PMOS body bias voltage upon receiving the positive supply voltage and the PMOS reference voltage. The circuit also includes a NMOS body bias circuit including a NMOS charge pump for generating a negative supply voltage, a NMOS reference voltage generator for providing a NMOS reference voltage, and a NMOS linear voltage regulator circuit for generating a NMOS body bias voltage upon receiving the negative supply voltage and the NMOS reference voltage. The PMOS body bias voltage and the NMOS body bias voltage drive bulk of PMOS and NMOS devices in the integrated circuit.
申请公布号 US8416011(B2) 申请公布日期 2013.04.09
申请号 US20100941104 申请日期 2010.11.08
申请人 CHOKKA SRINIVAS REDDY;SAWARKAR PRASAD;LSI CORPORATION 发明人 CHOKKA SRINIVAS REDDY;SAWARKAR PRASAD
分类号 G05F1/575;G05F1/585;H02M3/10 主分类号 G05F1/575
代理机构 代理人
主权项
地址