发明名称 Calibration scheme for resolution scaling, power scaling, variable input swing and comparator offset cancellation for flash ADCs
摘要 In one embodiment, a comparator of a Flash analog-to-digital converter (ADC) is calibrated in the background by switching the comparator to a feedback loop, determining the comparator's current reference level, and adjusting the comparator's reference level to a target reference level by charging a reference capacitor coupled the comparator.
申请公布号 US8416106(B2) 申请公布日期 2013.04.09
申请号 US201113090501 申请日期 2011.04.20
申请人 THACHILE PRADIP;FUJITSU LIMITED 发明人 THACHILE PRADIP
分类号 H03M1/10 主分类号 H03M1/10
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