<p>A first layer (2) has n-type conductivity. A second layer (3) is a layer that is epitaxially formed on the first layer (2) and has p-type conductivity. A third layer (4) is a layer that is formed on the second layer (3) and has n-type conductivity. When the donor impurity concentration is defined as ND, the acceptor impurity concentration is defined as NA and the position in the depth direction from the interface between the first layer (2) and the second layer (3) toward the first layer (2) is defined as D1, the value of D1 at which 1 <= ND/NA <= 50 is satisfied is 1 mum or less. A gate trench (6), which penetrates the third layer (4) and the second layer (3) and reaches the first layer (2), is provided. A gate insulating film (8) covers the side wall of the gate trench (6). A gate electrode (9) is embedded in the gate trench (6) with the gate insulating film (8) therebetween.</p>
申请公布号
WO2013046924(A1)
申请公布日期
2013.04.04
申请号
WO2012JP69790
申请日期
2012.08.03
申请人
SUMITOMO ELECTRIC INDUSTRIES, LTD.;WADA, KEIJI;MASUDA, TAKEYOSHI;HIYOSHI, TORU