发明名称 WIRING LAYOUT DESIGN METHOD, SEMICONDUCTOR DEVICE, AND PROGRAM THAT SUPPORTS WIRING LAYOUT DESIGN
摘要 <P>PROBLEM TO BE SOLVED: To provide a wiring layout design method capable of achieving high integration, a semiconductor device, and a program that supports the design of a wiring layout. <P>SOLUTION: A wiring layout design method according to an embodiment, which is a method of designing a layout formed by a side-wall method, includes the steps of: preparing a base pattern in which a plurality of first patterns that extend in a first direction and are arranged at a first interval in a second direction crossing in the first direction and a plurality of second patterns that extend in the first direction and arranged at each center between the first patterns; and connecting two of the adjacent first patterns sandwiching one of the second patterns with a pattern extending in the second direction and replacing the one of the second patterns with two patterns that do not contact the two of the first patterns. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013061575(A) 申请公布日期 2013.04.04
申请号 JP20110201230 申请日期 2011.09.14
申请人 TOSHIBA CORP 发明人 KODAMA CHIKAAKI;NAKAYAMA KOICHI;KOTANI TOSHIYA;NOJIMA SHIGEKI
分类号 G03F1/68;H01L21/027;H01L21/3205;H01L21/768;H01L23/522 主分类号 G03F1/68
代理机构 代理人
主权项
地址