发明名称 CACHE AND/OR SOCKET SENSITIVE MULTI-PROCESSOR CORES BREADTH-FIRST TRAVERSAL
摘要 Methods, apparatuses and storage device associated with cache and/or socket sensitive breadth-first iterative traversal of a graph by parallel threads, are disclosed. In embodiments, a vertices visited array (VIS) may be employed to track graph vertices visited. VIS may be partitioned into VIS sub-arrays, taking into consideration cache sizes of LLC, to reduce likelihood of evictions. In embodiments, potential boundary vertices arrays (PBV) may be employed to store potential boundary vertices for a next iteration, for vertices being visited in a current iteration. The number of PBV generated for each thread may take into consideration a number of sockets, over which the processor cores employed are distributed. In various embodiments, the threads may be load balanced; further data locality awareness to reduce inter-socket communication may be considered, and/or lock-and-atomic free update operations may be employed. Other embodiments may be disclosed or claimed.
申请公布号 US2013086354(A1) 申请公布日期 2013.04.04
申请号 US201213629087 申请日期 2012.09.27
申请人 SATISH NADATHUR RAJAGOPALAN;KIM CHANGKYU;CHHUAGANI JATIN;SEWALL JASON D. 发明人 SATISH NADATHUR RAJAGOPALAN;KIM CHANGKYU;CHHUAGANI JATIN;SEWALL JASON D.
分类号 G06F15/80 主分类号 G06F15/80
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