| 摘要 |
A vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure are provided. The vertical selection transistor comprises: an upper electrode; a lower electrode (BL1); a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode (BL1) and the upper electrode; and a gate stack (5) formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer and the third semiconductor layer respectively. |
