| 摘要 |
A plurality of pulse width modulation (PWM) generators are provided, each having a separate phase offset counter to create a phase shift instead of using either a time base counter preload value or an adder to create the phase shift offset relative to the PWM time base and the duty cycle. The phase shifting process is separated from the duty cycle generation process, thereby easing the task of preserving the duty cycle and phase relationships among the various PWM channels following an asynchronous external synchronization event. At least one master time base generates a PWM cycle start signal that resets the phase offset counters in each of the PWM generator circuits. The phase offset counter continues counting until it matches the respective phase offset value. At that time, the associated duty cycle counter is reset and restarted. The duty cycle continues until its count matches the specified duty cycle value at which time the duty cycle counter stops until reset by the terminal count from the phase offset counter. The output of the duty cycle comparators provide the output PWM signals as a repetitive series of single cycle PWM signals. |
