| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce power consumption during testing while suppressing increase in the circuit scale of a semiconductor integrated circuit equipped with a clock gating circuit. <P>SOLUTION: A semiconductor integrated circuit of the invention comprises: a first flip-flop circuit 5; a second flip-flop circuit 7; a control circuit 3; and a clock gating circuit 2. The first flip-flop 5 stores first data by scan shift. The second flip-flop 7 stores second data by scan shift. The control circuit 3 outputs, as a gate control signal C1, the result of a logical operation between the following two logical operation results: the result of a logical operation between the first data and a scan-enable signal SMC; and the result of a logical operation between the second data and a first enable signal EN1 that is output from a combination circuit 9. The clock gating circuit 2 controls the transmission of a clock signal CLK to a next-stage flip-flop circuit 1 according to the gate control signal C1. <P>COPYRIGHT: (C)2013,JPO&INPIT |
