An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes.
申请公布号
WO2013048522(A1)
申请公布日期
2013.04.04
申请号
WO2011US54471
申请日期
2011.10.01
申请人
INTEL CORPORATION;CHILDS, MICHAEL A.;FISCHER, KEVIN J.;NATARAJAN, SANJAY S.
发明人
CHILDS, MICHAEL A.;FISCHER, KEVIN J.;NATARAJAN, SANJAY S.