发明名称 PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF
摘要 PURPOSE: A package substrate and a manufacturing method thereof are provided to reduce the manufacturing costs and time by removing a copper plating process on the upper and lower sides of a base substrate and the inner side of a via hole. CONSTITUTION: A circuit pattern(110) is formed on the upper side of a base substrate(100). The base substrate is composed of a copper laminate plate. A plurality of via holes(121) are formed on the base substrate for interlayer conduction. The via is formed by filling the inner side of the via hole with conductive paste without a copper plating process. A solder bump(200) surrounds a protrusive part(122) of the via. A solder resist layer(130) is formed on the upper and lower sides of the base substrate to protect the circuit pattern.
申请公布号 KR20130033160(A) 申请公布日期 2013.04.03
申请号 KR20110097066 申请日期 2011.09.26
申请人 SAMSUNG ELECTRO-MECHANICS CO., LTD. 发明人 MOK, JEE SOO
分类号 H01L23/48;H01L21/60;H01L23/12 主分类号 H01L23/48
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