发明名称 |
MASK LEVEL REDUCTION FOR MOFET |
摘要 |
<p>A method of fabricating a thin film transistor for an active matrix display using reduced masking operations includes patterning a gate on a substrate. A gate dielectric is formed over the gate and a semiconducting metal oxide is deposited on the gate dielectric. A channel protection layer is patterned on the semiconducting metal oxide overlying the gate to define a channel area and to expose the remaining semiconducting metal oxide. A source/drain metal layer is deposited on the structure and etched through to the channel protection layer above the gate to separate the source/drain metal layer into source and drain terminals and the source/drain metal layer and the semiconducting metal oxide are etched through at the periphery to isolate the transistor. A nonconductive spacer is patterned on the transistor and portions of the surrounding source/drain metal layer.</p> |
申请公布号 |
EP2497107(A4) |
申请公布日期 |
2013.04.03 |
申请号 |
EP20100828708 |
申请日期 |
2010.09.09 |
申请人 |
CBRITE INC. |
发明人 |
SHIEH, CHAN-LONG;FOONG, FATT;YU, GANG |
分类号 |
H01L21/336;H01L27/12;H01L29/49;H01L29/66;H01L29/78;H01L29/786 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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