| 摘要 |
An integrated circuit includes IP (Intellectual Property) cores and intermediary circuits. The intermediary circuits are each connected to one IP core among the IP cores, and relay, using an NoC (Network On Chip) scheme, packets transmitted/received between the IP cores. The intermediary circuits are connected to each other. Each of the intermediary circuits replaces, when the intermediary circuit has received flow-control packets which are each transmitted from one IP core to another IP core in order to notify the other IP core of free-space information of a data buffer which the one IF core has, in a case where destinations of the flow-control packets are the same IP core, the flow-control packets with one flow-control packet including the free-space information included in the flow-control packets, and transmits the one flow-control packet to the IP core which is the destination.
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