发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE: A PLL(Phase-Locked Loop) circuit is provided to be stably operated in poor conditions such as instantaneous voltage drops of a power supply, harmonics, phase angle jumps, etc. CONSTITUTION: A PLL circuit(10) includes a d-q conversion part(11), a normalization part(12), an ALC(Adaptive Linear Combiner) part(13), and a PI(Proportional Integral) control part(14). The d-q conversion part receives three-phase signals and produces stationary signals of d-axis and q-axis. The normalization part normalizes the output of the d-q conversion part. The ALC part outputs an estimated vector by applying a weighted value, calculated with a delta rule, to the normalized d-q stationary signals. The PI control part receives the output of the ALC part and minimizes errors. [Reference numerals] (11) D-q conversion part; (13) ALC part; (14) PI control part;
申请公布号 KR20130032429(A) 申请公布日期 2013.04.02
申请号 KR20110096009 申请日期 2011.09.23
申请人 LSIS CO., LTD. 发明人 LEE, HYE YEON;BAE, BYUNG YEOL
分类号 H03L7/08;H03L7/00 主分类号 H03L7/08
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