发明名称 |
Global synchronization of parallel processors using clock pulse width modulation |
摘要 |
A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system. |
申请公布号 |
US8412974(B2) |
申请公布日期 |
2013.04.02 |
申请号 |
US20100696764 |
申请日期 |
2010.01.29 |
申请人 |
CHEN DONG;ELLAVSKY MATTHEW R.;FRANKE ROSS L.;GARA ALAN;GOODING THOMAS M.;HARING RUDOLF A.;JEANSON MARK J.;KOPCSAY GERARD V.;LIEBSCH THOMAS A.;LITTRELL DANIEL;OHMACHT MARTIN;REED DON D.;SCHENCK BRANDON E.;SWETZ RICHARD A.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHEN DONG;ELLAVSKY MATTHEW R.;FRANKE ROSS L.;GARA ALAN;GOODING THOMAS M.;HARING RUDOLF A.;JEANSON MARK J.;KOPCSAY GERARD V.;LIEBSCH THOMAS A.;LITTRELL DANIEL;OHMACHT MARTIN;REED DON D.;SCHENCK BRANDON E.;SWETZ RICHARD A. |
分类号 |
G06F1/04;G06F1/12;G06F15/16 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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