发明名称 Direct memory access transfer efficiency
摘要 A mechanism is provided for improving the efficiency of multiple smaller direct memory access transfers. The mechanism uses one input buffer and a small result buffer, or some temporary variables, to temporarily store computation results. The mechanism performs a computation on a segment of data in the input buffer and stores the result in the temporary result buffer. The mechanism then copies the result back into the input buffer. As such, the mechanism uses the input buffer as both an input buffer and a results buffer. The mechanism then performs a direct memory access transfer on the segment of the input buffer that contains the computation result and then performs a computation on the next segment of the input buffer. The mechanism then repeats this process until the entire input buffer has been processed.
申请公布号 US8412862(B2) 申请公布日期 2013.04.02
申请号 US20080337703 申请日期 2008.12.18
申请人 LU JIZHU;PERRONE MICHAEL P.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 LU JIZHU;PERRONE MICHAEL P.
分类号 G06F3/00 主分类号 G06F3/00
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