发明名称 |
DELAY LOCKED LOOP BASED FREQUENCY MULTIPLYING APPARATUS AND METHOD WITH DETECTING AND RESOLVING HARMONIC LOCK |
摘要 |
PURPOSE: A delay synchronization loop based frequency multiplication device and a frequency multiplication method are provided to prevent performance degradation due to an initial bias time. CONSTITUTION: A frequency multiplication device(601) includes a delay unit(603), a provision unit(605), and a recovery unit(606). The delay unit generates an output clock by delaying an input clock of the frequency multiplication device by a delay time. The recovery unit detects generation of harmonic lock of the frequency multiplication device and recovers harmonic lock. The provision unit provides a pulse to multiply a frequency of the frequency multiplication unit. [Reference numerals] (602) Selection unit; (603) Delay unit; (604) Control unit; (605) Provision unit; (606) Recovery unit; (607) Sensing unit; (608) Comparison unit; (609) Generating unit; (AA) Input signal; (BB) Output signal; |
申请公布号 |
KR101248718(B1) |
申请公布日期 |
2013.04.02 |
申请号 |
KR20120031894 |
申请日期 |
2012.03.28 |
申请人 |
HONGIK UNIVERSITY INDUSTRY-ACADEMIA COOPERATION FOUNDATION |
发明人 |
KIM, JONG SUN;LEE, SUNG KEUN |
分类号 |
H03B19/00;H03L7/081 |
主分类号 |
H03B19/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|