发明名称 |
PROCESSOR AND CONTROL METHOD OF PROCESSOR |
摘要 |
A processor includes: first selectors that select instruction addresses of instructions of a plurality of threads or a branch target address of a branch instruction to be predicted and that output addresses of the plurality of threads; a second selector that selects one of the addresses of the plurality of threads output by the first selectors; a branch prediction circuit that predicts and outputs a branch direction, which indicates whether the branch instruction of the address selected by the second selector is branched, based on the selected address in a first cycle stage and that predicts and outputs the branch target address of the branch instruction to be predicted based on the selected address in a second cycle stage later than the first cycle stage; and a thread arbitration circuit that controls selection of the addresses of the threads by the first selectors and the second selector.
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申请公布号 |
US2013080749(A1) |
申请公布日期 |
2013.03.28 |
申请号 |
US201213591383 |
申请日期 |
2012.08.22 |
申请人 |
ITO TOSHIRO;SUZUKI TAKASHI;FUJITSU LIMITED |
发明人 |
ITO TOSHIRO;SUZUKI TAKASHI |
分类号 |
G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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