发明名称
摘要 A cryptography circuit protected by masking, said circuit including means for encrypting binary words using at least one key krc, means for applying linear processing operations and nonlinear processing operations to said words and means for masking said words. The binary words are unmasked upstream of the nonlinear processing operations by using a mask kri and masked downstream of said processing operations by using a mask kr+1i, the masks kri and kr+1i being chosen from a set of masks that is specific to each instance of the circuit.
申请公布号 JP2013511057(A) 申请公布日期 2013.03.28
申请号 JP20120538299 申请日期 2010.11.08
申请人 发明人
分类号 G09C1/00 主分类号 G09C1/00
代理机构 代理人
主权项
地址