发明名称 |
LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE |
摘要 |
In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5x1019 (atoms /cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.Figure 1 |
申请公布号 |
SG188112(A1) |
申请公布日期 |
2013.03.28 |
申请号 |
SG20130008669 |
申请日期 |
2010.10.06 |
申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
发明人 |
SHIONOIRI, YUTAKA;KOBAYASHI, HIDETOMO |
分类号 |
|
主分类号 |
|
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|