发明名称 ADDRESS TRANSLATION DEVICE, PROCESSING DEVICE AND CONTROL METHOD OF PROCESSING DEVICE
摘要 An address translation buffer (TLB) which holds pairs of virtual addresses and physical addresses by respective page sizes and performs an address translation, a storage unit which holds a pair of a virtual address removed from the TLB and page size corresponding thereto when a pair of a new virtual address and physical address read from a page table is registered to the TLB, base registers which hold a base address by each page size are held. The TLB is searched based on a translation object virtual address included in a memory access request, and when a TLB miss occurs, a main storage is searched based on a pointer address generated from information held by the storage unit and the base register, and the translation object virtual address is translated into the physical address.
申请公布号 US2013080735(A1) 申请公布日期 2013.03.28
申请号 US201213562414 申请日期 2012.07.31
申请人 KIMURA HIROAKI;FUJITSU LIMITED 发明人 KIMURA HIROAKI
分类号 G06F12/10 主分类号 G06F12/10
代理机构 代理人
主权项
地址