| 摘要 |
Circuits and methods for full rate data reception and transmission using half-frequency clock signals are disclosed. In one embodiment, a flop circuit includes a data input, a data output, and a clock input. The clock signal has a first frequency, while the flop circuit is configured to output data at a rate corresponding to a second frequency. In one embodiment, the second frequency is twice the first frequency. The flop circuit is configured to transmit a first data bit responsive to a first edge (e.g., a rising edge) of the clock signal and a second data bit responsive to a second edge (e.g., a falling edge) of the clock signal that is the next edge following the first edge. Accordingly, the flop circuit may effectively operate at the second frequency utilizing the clock signal at the first lower frequency.
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