发明名称 |
Method for Three Dimensional Integrated Circuit Fabrication |
摘要 |
A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.
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申请公布号 |
US2013075892(A1) |
申请公布日期 |
2013.03.28 |
申请号 |
US201113246553 |
申请日期 |
2011.09.27 |
申请人 |
LIN JING-CHENG;WU WENG-JIN;SHIH YING-CHING;HUNG JUI-PIN;LU SZU WEI;JENG SHIN-PUU;YU CHEN-HUA;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LIN JING-CHENG;WU WENG-JIN;SHIH YING-CHING;HUNG JUI-PIN;LU SZU WEI;JENG SHIN-PUU;YU CHEN-HUA |
分类号 |
H01L23/48;H01L21/50 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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地址 |
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