发明名称 FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
摘要 <P>PROBLEM TO BE SOLVED: To provide a flexible AES instruction set for a general purpose processor. <P>SOLUTION: An AES instruction set includes instructions to perform a "one round" pass for AES encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible AES instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013057946(A) 申请公布日期 2013.03.28
申请号 JP20120226077 申请日期 2012.10.11
申请人 INTEL CORP 发明人 SHAY GUERON;WAJDI K FEGHALI;VINODH GOPAL;MAKARAM RAGHUNANDAN;MARTIN G DIXON;SRINIVAS CHENNUPATY;MICHAEL E KOUNAVIS
分类号 G09C1/00 主分类号 G09C1/00
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