发明名称 |
SEMICONDUCTOR DEVICE INCLUDING DLL CIRCUIT HAVING COARSE ADJUSTMENT UNIT AND FINE ADJUSTMENT UNIT |
摘要 |
Disclosed herein is a device that includes a coarse adjusting circuit generating first and second clock signals having different phases from each other, and a fine adjusting circuit generating a third clock signal having a phase between a phase of the first clock signal and a phase of the second clock signal. The fine adjusting circuit includes a plurality of first transistors receiving the first clock signal and a plurality of second transistors receiving the second clock signal. The fine adjusting circuit controls the phase of the third clock signal by synthesizing the first clock signal output from selected zero or more of the first transistors based on adjustment codes and the second clock signal output from selected zero or more of the second transistors based on the adjustment codes. The adjustment codes are not a binary system. |
申请公布号 |
US2013076413(A1) |
申请公布日期 |
2013.03.28 |
申请号 |
US201213612654 |
申请日期 |
2012.09.12 |
申请人 |
UEMURA YUTAKA;ELPIDA MEMORY, INC |
发明人 |
UEMURA YUTAKA |
分类号 |
H03L7/08 |
主分类号 |
H03L7/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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